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What are the top-3 challenges in IP/MPLS router design ?

If you are familiar with MPLS label switching operations and IP routing operations you might wonder: how come router are so expensive whereas the operations they perform are relatively simple? In this post, I will show you where the complexity of router design lies, and I will highlight the current challenges in router design.

Let's start by the most important point: yes, IP and MPLS routing operations are simple. By design, they seek efficiency, to enable supporting larger and larger traffic amounts. But current interfaces reach 100Gb/s per slot. A large router can support several dozen of 100Gb/s ports. That makes a lot of traffic! Supporting such speeds of operations is the challenge for router designers!

Let's see what current 100Gb/s interfaces imply for router hardware:

  1. Integrate more features on ASICs 
    • Complex packet parsing and deep packet header inspection 
    • Variety of forwarding protocols (L2, IP, MPLS, etc.) 
    • Current lithography techniques at 14 nanometers scale 
  2. Provide bigger, faster, less energy-hungry memories, to implement queues for QoS 
    • 100GbE interfaces
      • need to read about 150 million packets per second (Mpps) in memory, i.e. read a packet in a few nanoseconds 
    • Provide faster communications between inbound, service, and outbound cards •Crossbar instead of buses, etc.
litography generations (src : wikipedia)
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